Tutorial Information

Full-Day Tutorials, Sunday, August 6, 2017, 9am – 4:30pm

Supercapacitor Based Embedded Energy Harvesters

Instructor: Prof. Tolga Soyata, Department of Electrical and Computer Engineering, SUNY Albany, USA
Tutorial Overview: Autonomous field systems that operate in the 1–10W range typically use rechargeable batteries due to the ease in deployment, because energy harvesting ICs are readily available for solar input, as well as Li-Ion battery-based energy buffering. However, supercapacitors have only recently been used in autonomous field harvesters; standard solutions are only available for the microWatt ot milliWatt power range, not for the 1–10W range that most embedded field devices require. In this tutorial, we provide a background for the operational theory of supercapacitors, their advantages and disadvantages as compared to the rechargeable batteries and demonstrate a working solar energy harvester that uses a supercapacitor as its sole energy buffer. For the demonstrations, an open-source energy harvester, designed by the speaker’s research group is used.
Session I: In this session, we will provide a detailed overview of the fundamental attributes of supercapacitors including modeling, round trip efficiency, cost analysis, lifetime considerations, environmental friendliness, and energy predictability.
Session II: In this session of the tutorial, we will compare the main features of supercapacitors —explained in the previous section— with conventional Li-ion batteries. This comparison will reveal the aspects in which supercapcitors are superior to batteries and why battery-based energy buffers might be preferred for certain applications.
Session III: In the third section of this tutorial, we will investigate ambient energy harvesting schemes, in which supercapacitors have been increasingly used as the primary energy buffer. We will commence our discussion by reviewing different types of power harvesters and their applications in commerce and research including ultra-low-power harvesters used in Wireless Sensor Networks, medium-power harvesters utilized in Cyber Physical Systems, and high-power grid-connected energy harvesters.
Session IV: In the last section of our tutorial, we will introduce UR-SolarCap, an open source ready-to-use supercapacitorbased solar energy harvester as a case study of harvesting systems. Based on our guidelines given in the previous sections, we will identify different components of this harvester’s architecture and investigate their implementation in UR-SolarCap.
At the end of this tutorial, we will overview related work, future work and possible advances in supercapacitor-related technologies.

IC Power Management Circuits and Systems with Emphasis for Portable Devices

Instructors: Prof. Jose Silva-Martinez and Prof. Edgar Sánchez-Sinencio, Department of Electrical and Computer Engineering, Texas A&M University, USA
Tutorial Overview: This tutorial course in Integrated Circuits Power Management will give an overview of the major aspects of DC-DC linear regulators, switching regulators (buck and boost) and battery chargers. Also discussion on battery wireless battery charges will be included. Power management (a $13B global market soon growing to $70B within a decade) plays a crucial role in the technology development of many consumer electronics: Cell-phones, Laptop computers, PDAs, Flat screen monitors, digital TVs, Military and Aerospace systems. Emphasis will be placed on the mathematical foundations as well as on the analysis and design of key power electronic building blocks, namely: Feedback theory, stability and root locus, multi-stage amplifiers, design of dc to dc and ac to dc converters, power supplies, and battery chargers. Time variant envelope tracking switching regulators for PA power added efficiency optimization will be included.

Half-Day Tutorials, Sunday, August 6, 2017, 9am – 12pm

Switching Noise Mitigation for Integrated DC-DC Converters

Instructor: Prof. Ayman Fayed, Department of Electrical and Computer Engineering, The Ohio State University, USA
Tutorial Overview: Mobile communication and navigation devices have fueled the demand for low power implementations to enhance battery life. A critical aspect of reducing power in these devices is the efficiency of the process of converting power from the battery to the various loads in the system. This makes high-efficiency DC-DC switching power converters a natural candidate for such task. Unfortunately, however, with the high level of integration of many noise-sensitive analog/RF circuits within these devices, the ability to use and integrate these DC-DC power converters is severely limited due to the large switching noise they generate, which tends to degrade the performance of analog/RF circuits. This forces the use of alternative, inefficient, but low-noise power converters such as linear regulators, and/or large passive components for switching noise suppression. These alternative techniques reduce battery life and increase implementation cost. This tutorial will start by introducing the basic operation of DC-DC power converters and the spectral characteristics of the switching noise they generate with different types of control schemes, such as PWM, PFM, and hysteretic control schemes during DCM and CCM operation modes. This will be followed by introducing the various mechanisms by which this switching noise can couple into and degrade the performance of noise sensitive loads in large SoCs, either directly through powering of these loads, or indirectly through shared power pins and substrate. An overview of conventional switching noise mitigation techniques employed in DC-DC converters will then follow, including techniques such as post linear regulation, active ripple cancellation, multi-phase converters, delta-sigma control, and frequency hopping/stepping. Spread-spectrum and spur-free control techniques that fully eliminate spurious noise in DC-DC converters will then be presented.

Hybrid Microfluidic CMOS Systems for Life Science Applications

Instructors: Prof. Ebrahim Ghafar-Zadeh and Prof. Sebastian Magierowski, Department of Electrical Engineering and Computer Science, York University, Canada
Tutorial Overview: CMOS microelectronics has received significant interest as a platform for developing microsystem-based biosensors suitable for numerous life science applications including point-of-care diagnostics, drug discovery and DNA sequencing. In this tutorial, after an overview of CMOS bio-sensing techniques, we will focus on two applications of
CMOS technologies in the life science context: drug discovery and DNA sequencing. CMOS solutions for two specific life science applications will be introduced: Drug Discovery Platforms and DNA Sequencing. Drug discovery is a costly and time consuming undertaking. Two promising CMOS solutions are offered that respectively leverage capacitive sensors and
nuclear magnetic resonance (NMR) techniques. Microfluidic Devices: play an essential role in directing micro or nano-liter sized sample solutions toward sensing sites on the top of CMOS chips. To date many techniques have been proposed to develop microfluidic devices and integrate these on the top of CMOS chip using hermetic bonding techniques. Among these
techniques, this tutorial reviews the practical and efficient microfluidic techniques for researchers who are interested in CMOS biosensor applications.

Ultra-low Power/Energy SRAM Design for Internet-of-Things

Instructor: Prof. Tony Tae-Hyoung Kim, School of Electrical and Electronic Engineering, Nanyang Technological University, Singapore
Tutorial Overview: Recently, various ultra-low power applications such as Internet-of-Things (IoT), wearable devices, and biomedical devices have emerged opening up a new domain of integrated circuits design. In these applications, ultra-low voltage circuit techniques for improving the power and energy efficiencies have been the main research focus. One of the most challenging functional blocks in ultra-low power systems is memory where SRAMs are dominantly employed. Since SRAMs occupy majority of the power in those systems, design of ultra-low power SRAMs is a critical task for power and energy efficiencies. One of the most popular SRAM design methodology for ultra-low power applications is using aggressively scaled supply voltage. However, this deteriorates various SRAM design parameters such as stability, sensing margin, write margin, etc. Various techniques for ultra-low voltage SRAMs have been reported to tackle the limitations at ultra-low voltage operation. This tutorial will provide the basics in ultra-low voltage SRAMs followed by the trend in various state-of-the-art ultra-low voltage SRAMs. More detailed ultra-low voltage SRAM design works developed by the author’s group will also be explained. Finally, we will discuss future directions in ultra-low voltage SRAMs including various emerging non-volatile memory devices such as Flash, STTRAM, RRAM, etc.

Half-Day Tutorials, Sunday, August 6, 2017, 1:30pm – 4:30pm

Signal Integrity Challenges in Emerging DDR Technologies

Instructors: Sri Garimella, Dr Selim Guncer, Dr. Andreas Falkenberg, Ostendo Technologies, USA
Tutorial Overview: Advancements in Microprocessor technologies and Double Data Rate (DDR) Memory capacity drives the need for a high speed and high performance DDR interface. The DDR interface should be capable of supporting a huge memory capacity over a wide channel at high speeds to scale with the advancements in processor memory bandwidth requirements. However, scaling of IO bandwidth is constrained by off-chip interconnect technology and multi-chip memory loads and increasingly noisy on/off-chip environment which leads to Signal Integrity (SI) problems. Signal Integrity issues such as cross-talk, reflection, signal attenuation, channel loss, edge alignment, SSO, ISI etc. have become challenging for Interface designers. For emerging DDR IO technologies such as DDR4 and DDR5, signal integrity improvement techniques are increasingly more relavant in the design flow . The high speed DDR IO design that meets the requirements of different standards becomes an attractive design proposition. In this tutorial the DDR memory architectures are introduced,- Specifically DDR4 and DDR5 IO technologies and the respective Signal Integrity challenges are discussed in more detail. Simulation results are presented to illustrate the impact of off-chip loads and interconnects on the IO performance and link margins. The IO circuit design techniques to improve the performance are discussed.

Synthesis of BTI Reliable CMOS VLSI Systems in Nanometer Technologies

Instuctor: Prof. Srinivas Katkoori, Department of Computer Science and Engineering, University of South Florida, USA
Tutorial Overview: Aggressive CMOS technology scaling resulted in today’s nanoscale technology nodes that facilitated the integration of billions of transistors on a single integrated circuit (IC). In nanoscale technology nodes, reliability issues arise due to various physical phenomena such as soft-errors, Bias Temperature Instability (BTI), interconnect crosstalk, thermal distribution, and process variations. In this half-day tutorial, we will focus on the BTI related reliability issues. Negative Bias Temperature Instability (NBTI) effect occurs in a PMOS transistor when turned ON leading to threshold voltage degradation thereby causing performance degradation as the circuit ages. According to ITRS 2013, NBTI degradation problem has become increasingly significant as Vt is aggressively scaled down to reduce the sub-threshold leakage power. Further, the introduction of high-k gateoxide worsens the NBTI problem. It is shown that for ultra-thin gate oxide layers (about 4nm), NBTI effect in PMOS devices can result in as much as 15% circuit degradation over 10 year lifetime. With the current trend of even thinner oxide layers, we can only expect NBTI to get worse. Positive BTI (PBTI) is a complementary phenomenon that worsens NMOS transistors. The tutorial is organized into four parts: (a) introduction of basics of BTI phenomenon and estimation models, (b) synthesis and optimization techniques for BTI hardened circuits, (c) industry strength tools and design flows for BTI reliability optimization, and (d) future directions. Specific techniques that will be discussed in detailed include: BTI tolerant library design, gate-sizing, gate-replacement, input vector control, input vector cycling, and BTI and leakage co-optimization.

Neuromorphic and Compressing Computing Circuits and Systems

Instructors: Prof. Vishal Saxena, Department of Electrical and Computer Engineering, University of Idaho, USA; Prof. Subhanshu Gupta, Department of Electrical and Computer Engineering, Washington State University, USA
Tutorial Overview: In 2015, U. S. Office of Science and Technology (OSTP) announced a grand challenge which is supported by federal agencies and the IEEE: “Create a new type of computer that can proactively interpret and learn from data, solve unfamiliar problems using what is learned, and operate with the energy efficiency of the human brain.” In alignment with this, large-scale integration of CMOS mixed-signal integrated circuits and nanoscale emerging devices, such as the resistive RAM (RRAM), can enable a new generation of Neuromorphic computers that can be applied to a wide range of machine learning problems. This tutorial combines an overview of recent advances in energy-efficient Neuromorphic Computing circuits and systems, and sensor interfaces using compressive sensing (CS) architecture for embedded deep learning applications. The tutorial aims to provide a complete picture to the audience; starting from system level architecture to the transistor- and device-level design trade-offs. Case studies will be presented for Neuromorphic System-on-a-chip (NeuSoC) and CS architectures with applications to statistical learning followed by recent advances in the area of intelligent sensor nodes.